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Hardware
void DDR_UP(t_DDR_PARAMETERS* params)
{
unsigned int end;
volatile ddr_memc_map_t* ddr = (volatile ddr_memc_map_t*) DDR_BASE;
volatile clk_map_t* clk = (volatile clk_map_t*) CLK_BASE;
volatile btm_map_t* btm = (volatile btm_map_t*) BTM_BASE;
// STOPCTL - enable DDR clk
clk->STOPCTRL &= ~0x00003000;
// DEVCFG
if (params->WIDTH32 == 1)
{ btm->CHPCFG |= 0x00000020; } // 32-bit DDR
else
{ // 16-bit
btm->CHPCFG &= ~0x00000020;
if (btm->CHPCFG & 0x00000020) // Cannot be cleared
{ params->WIDTH32 = 1; }
}
// CSBR0
end = (params->START) + (params->BYTES - 1);
if (params->WIDTH32 == 1)
{ ddr->CS0_BNDS = (params->START >> 7) | (end >> 23); }
else
{ ddr->CS0_BNDS = (params->START >> 6) | (end >> 22); }
// CS0CFG
ddr->CS0_CONFIG = params->CS0CFG;
// TCFG1
ddr->TIMING_CFG_1 = params->TCFG1;
// TCFG2
ddr->TIMING_CFG_2 = params->TCFG2;
// SCFG (First Time)
ddr->DDR_SDRAM_CFG = (params->SCFG);
// SMCFG
ddr->DDR_SDRAM_MODE = params->SMCFG;
// SICFG
ddr->DDR_SDRAM_INTERVAL = params->SICFG;
// SCFG (Last Time)
ddr->DDR_SDRAM_CFG = (params->SCFG) | 0x80000000;
return;
}
3.3
Complex Programmable Logic Device (CPLD)
A Xilinx XC9572XL CPLD device implements chip-select logic and logic registers on the SPT711xPFCE
board. This device contains 72 macrocells and is programmed through JTAG signals on J10. The CPLD
self configures when reset is deasserted and does not require external configuration memory. For
information on this device, refer to the Xilinx web site (http://www.xilinx.com) .
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
12
Freescale Semiconductor
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